Write a verilog code for Mealy?

All Questions › Category: Verilog › Write a verilog code for Mealy?
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Chetan Shidling Staff asked 5 years ago

I need code.

1 Answers
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Chetan Shidling Staff answered 5 years ago

module mealyprog_tb;

// Inputs

reg CLK;
reg RST;
reg x;

// Outputs

wire z;

// Instantiate the Unit Under Test (UUT)

mealyprog uut (
.CLK(CLK),
.RST(RST),
.x(x),
.z(z)
);
initial begin

// Initialize Inputs

CLK = 0;
RST = 0;
x = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;

end
always @(x)
begin
forever #5 CLK=~CLK;
end
endmodule

//TEST BENCH

module mealyprog_tb;

// Inputs

reg CLK;
reg RST;
reg x;

// Outputs

wire z;

// Instantiate the Unit Under Test (UUT)

mealyprog uut (
.CLK(CLK),
.RST(RST),
.x(x),
.z(z)
);
initial begin

// Initialize Inputs

CLK = 0;
RST = 0;
x = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
end
always @(x)
begin
forever #5 CLK=~CLK;
end
endmodule