Write a verilog code for Booth Multiplier?

//BOOTH MULTIPLIER

module booth_mul(a,b,c);
input signed [3:0] a,b;
output reg signed [7:0] c;
reg [1:0] temp;
integer i;
reg e;
reg [3:0] y1;
always @(a,b)
begin
c=8’d0;
e=1’d0;
for(i=0;i<4;i=i+1)
begin
temp={a[i],e};
y1=-b;
case(temp)
2’d2:c[7:4]=c[7:4]+y1;
2’d1:c[7:4]=c[7:4]+b;
default :begin end
endcase
c=c>>1;
c[7]=c[6];
e=a[i];
if(b==4’d8)
begin
c=-c;
end
end
end
endmodule

//TEST BENCH

module booth_tf;

// Inputs

reg [3:0] a;
reg [3:0] b;

// Outputs

wire [7:0] c;

// Instantiate the Unit Under Test (UUT)

booth_mul uut (
.a(a),
.b(b),
.c(c)
);
initial begin

// Initialize Inputs

a = 0;
b = 0;
#100;

// Add stimulus here

a = 2;
b = 2;
#100;
a = 3;
b = 4;
#100;
end

endmodule