Write a verilog code for encoder?

//ENCODERS

module encoders(y,x,en);
input en;
input [7:0] x;
output [2:0] y;
assign y[2]=en&(x[4]|x[5]|x[6]|x[7]);
assign y[1]=en&(x[2]|x[3]|x[6]|x[7]);
assign y[0]=en&(x[1]|x[3]|x[5]|x[7]);
endmodule

//TEST BENCH

module Encoders_tb;

// Inputs

reg [7:0] x;
reg en;

// Outputs

wire [2:0] y;

// Instantiate the Unit Under Test (UUT)

encoders uut (
.y(y),
.x(x),
.en(en)
);
initial begin

// Initialize Inputs

x = 0;
en = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

en=1;
x=8’b00000001;
#100;
x=8’b00000010;
#100;
x=8’b00000100;
#100;
x=8’b00000100;
end

endmodule