Write a verilog code for full adder?

//FA

module full_ADDER(sum,carry,a,b,c);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=a&b|b&c|c&a;
endmodule

//TEST BENCH

module FULL_ADDER_tf;

// Inputs

reg a;
reg b;
reg c;

// Outputs

wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

full_ADDER uut (
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.c(c)
);
initial begin

// Initialize Inputs

a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a = 0;
b = 0;
c = 0;
#100;
a = 0;
b = 0;
c = 1;
#100;
a = 0;
b = 1;
c = 0;
#100;
a = 1;
b = 1;
c = 1;
#100;
end

endmodule