VLSI CMOS Archives - Page 2 of 3 - CS Electrical & Electronics

All Questions › Category: VLSI CMOS

Filter:All Open Resolved Closed Unanswered
What is high to low transition in CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
596 views1 answers0 votes
What is low to high transition in CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
385 views1 answers0 votes
What is full form of NML in CMOS VLSI?
Openchetan shidling asked 4 years ago • VLSI CMOS
266 views0 answers0 votes
What is full form of NMH in CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
439 views1 answers0 votes
What is full form of ViH in CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
566 views1 answers0 votes
What is full form of ViL in inverter dc characteristics of CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
451 views1 answers0 votes
What is full form of VoL in inverter dc characteristics of CMOS VLSI?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
429 views1 answers0 votes
What is full form of VoH in inverter dc characteristics?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
362 views1 answers0 votes
What are companies which are hiring for VLSI engineers?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
378 views1 answers0 votes
What is demand for VLSI engineers?
AnsweredNitin asked 4 years ago • VLSI CMOS
416 views1 answers0 votes
What are the limitation of Dynamic CMOS logic?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
1028 views1 answers0 votes
Explain the working of clocked CMOS logic circuit?
Openchetan shidling asked 4 years ago • VLSI CMOS
530 views0 answers0 votes
Compare static CMOS logic and Pseudo NMOS logic with an example?
Openchetan shidling asked 4 years ago • VLSI CMOS
333 views0 answers0 votes
What is full form of CPL in VLSI CMOS?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
1092 views1 answers0 votes
What is full form of CVSL in VLSI CMOS?
Answeredchetan shidling asked 4 years ago • VLSI CMOS
693 views1 answers0 votes
Draw the Stick-diagram for the Boolean functions?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
388 views0 answers-1 votes
Draw the stick-diagram for the Boolean expression?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
409 views0 answers0 votes
What are the objectives for Euler path and Stick Diagrams?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
577 views1 answers0 votes
Expression for simple delay model for CMOS gates?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
389 views1 answers0 votes
What are the factors by which time delay of the Gate is affected?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
370 views1 answers0 votes
What is the worst case propagation delay of the circuit?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
625 views1 answers0 votes
R = 10K, C=0.1pF, then the buffer will experience a delay of Td ?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
385 views1 answers0 votes
What is RC model in CMOS VLSI circuits?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
293 views0 answers0 votes
What is propagation delay in CMOS VLSI circuits?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
364 views1 answers0 votes
What is tpLH and tpHL in CMOS VLSI circuits?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
970 views1 answers0 votes
What is fall time in CMOS VLSI circuits ?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
387 views1 answers0 votes
What is Rise time in CMOS VLSI circuits?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
701 views1 answers0 votes
What is Gate delays in VLSI CMOS circuits?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
271 views0 answers0 votes
What are timing parameters in VLSI?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
367 views1 answers0 votes
Explain the characteristics of
OpenChetan Shidling asked 4 years ago • VLSI CMOS
271 views0 answers0 votes
Realize equations for Full adder, and draw the gate level representation and stick diagram using CMOS logic?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
330 views0 answers0 votes
With a neat diagram, explain the various timing parameters of a CMOS circuit?
AnsweredChetan Shidling asked 4 years ago • VLSI CMOS
789 views1 answers0 votes
State the objectives which are addressed using Euler’s path to draw stick-diagrams?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
244 views0 answers0 votes
Draw the stick-diagram for the following Boolean expression using Euler’s path?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
422 views0 answers0 votes
Draw the stick diagram of 4:1 MUX ?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
1152 views0 answers1 votes
Draw the stick-diagram of 2-input NAND gate and 2:1 MUX ?
OpenChetan Shidling asked 4 years ago • VLSI CMOS
1041 views0 answers0 votes
Which of the following statements is incorrect?
Answeredcs asked 4 years ago • VLSI CMOS
968 views1 answers0 votes
Which of the following is not an objective for using Euler's path to draw stick diagrams?
Answeredcs asked 4 years ago • VLSI CMOS
367 views1 answers0 votes
Which of the following is not true about Latch-up in CMOS circuits?
Answeredcs asked 4 years ago • VLSI CMOS
346 views1 answers0 votes
In clocked CMOS logic, output in evaluated in?
Answeredcs asked 4 years ago • VLSI CMOS
778 views1 answers0 votes
In the equivalent circuit for PMOS, if the sheet resistance is 20Kohm and width of MOS is 4, then the Drain-Source resistance when the PMOS is ON is numerically equal to?
Answeredcs asked 4 years ago • VLSI CMOS
407 views1 answers0 votes
Pseudo-nMOS has higher pull-up resistance than nMOS device?
Answeredcs asked 4 years ago • VLSI CMOS
387 views1 answers0 votes
Pull Down Network will conduct for all input combinations that requires output Y to be
Answeredcs asked 4 years ago • VLSI CMOS
365 views1 answers0 votes
What is RC Extraction in CMOS VLSI?
Answeredcs asked 4 years ago • VLSI CMOS
604 views1 answers0 votes
What is full form of DRC in CMOS VLSI?
Answeredcs asked 4 years ago • VLSI CMOS
370 views1 answers0 votes
What is Latch-up in CMOS circuits?
Answeredcs asked 4 years ago • VLSI CMOS
402 views1 answers0 votes
What is precharge state in CMOS Dynamic logic?
Opencs asked 4 years ago • VLSI CMOS
320 views0 answers0 votes
What is evaluate state in CMOS Dynamic logic?
Opencs asked 4 years ago • VLSI CMOS
300 views0 answers0 votes
What is Clocked-CMOS logic?
Answeredcs asked 4 years ago • VLSI CMOS
467 views1 answers-1 votes
Difference between dynamic and static logic design?
Answeredcs asked 4 years ago • VLSI CMOS
461 views1 answers0 votes
What is Pseudo NMOS logic in CMOS VLSI?
Answeredcs asked 4 years ago • VLSI CMOS
525 views1 answers0 votes
What are the types of logic circuits in CMOS?
Answeredcs asked 4 years ago • VLSI CMOS
425 views1 answers0 votes
What type of MOS is preferable for PUN?
Opencs asked 4 years ago • VLSI CMOS
324 views0 answers0 votes
What type of MOS is preferable for PDN?
Opencs asked 4 years ago • VLSI CMOS
300 views0 answers0 votes
What is Complementary Logic design?
Answeredcs asked 4 years ago • VLSI CMOS
376 views1 answers0 votes
What is Complementary Logic design?
Opencs asked 4 years ago • VLSI CMOS
321 views0 answers0 votes
What is dynamic logic design?
Answeredcs asked 4 years ago • VLSI CMOS
680 views1 answers0 votes
What is static logic design?
Answeredcs asked 4 years ago • VLSI CMOS
697 views1 answers0 votes
What is combinational logic and non-regenerative circuits?
Answeredcs asked 4 years ago • VLSI CMOS
527 views1 answers0 votes
The chemical used for shielding the active areas to achieve selective oxide growth?
OpenChetan Shidling asked 5 years ago • VLSI CMOS
369 views0 answers0 votes
« Previous 123 Next »

Share Now