Questions Archives - Page 28 of 36

Warning: Trying to access array offset on false in /home3/indiakep/public_html/wp-content/plugins/dw-question-answer/inc/Template.php on line 8
All Questions › Category: Questions
Filter:All Open Resolved Closed Unanswered
What is try and catch blocks in exception handling?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
1169 views2 answers0 votes
What is catch block in exception handling?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
1018 views1 answers0 votes
What is try block in exception handling in Cpp?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
1026 views2 answers0 votes
What is syntax of try and catch block in exception handling in Cpp?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
951 views1 answers0 votes
What is catch keyword in exception handling in C++?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
854 views1 answers0 votes
What is throw keyword in exception handling in C++?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
856 views1 answers0 votes
What is try keyword in exception handling in C++?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
958 views1 answers0 votes
What is exception handling?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
917 views1 answers0 votes
What is an exception?
AnsweredChetan Shidling asked 6 years ago • Cpp Language
933 views1 answers0 votes
Draw the Stick-diagram for the Boolean functions?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
893 views0 answers-1 votes
Draw the stick-diagram for the Boolean expression?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
939 views0 answers0 votes
What are the objectives for Euler path and Stick Diagrams?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1406 views1 answers0 votes
Expression for simple delay model for CMOS gates?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
841 views1 answers0 votes
What are the factors by which time delay of the Gate is affected?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
861 views1 answers0 votes
What is the worst case propagation delay of the circuit?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1430 views1 answers0 votes
R = 10K, C=0.1pF, then the buffer will experience a delay of Td ?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
832 views1 answers0 votes
What is RC model in CMOS VLSI circuits?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
805 views0 answers0 votes
What is propagation delay in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
816 views1 answers0 votes
What is tpLH and tpHL in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1786 views1 answers0 votes
What is fall time in CMOS VLSI circuits ?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
835 views1 answers0 votes
What is Rise time in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1445 views1 answers0 votes
What is Gate delays in VLSI CMOS circuits?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
758 views0 answers0 votes
What are timing parameters in VLSI?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
809 views1 answers0 votes
Explain the characteristics of
OpenChetan Shidling asked 6 years ago • VLSI CMOS
730 views0 answers0 votes
Realize equations for Full adder, and draw the gate level representation and stick diagram using CMOS logic?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
851 views0 answers0 votes
With a neat diagram, explain the various timing parameters of a CMOS circuit?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1594 views1 answers0 votes
State the objectives which are addressed using Euler’s path to draw stick-diagrams?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
705 views0 answers0 votes
Draw the stick-diagram for the following Boolean expression using Euler’s path?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
923 views0 answers0 votes
Draw the stick diagram of 4:1 MUX ?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1816 views0 answers1 votes
Draw the stick-diagram of 2-input NAND gate and 2:1 MUX ?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1524 views0 answers0 votes
Which of the following statements is incorrect?
Answeredcs asked 6 years ago • VLSI CMOS
1453 views1 answers0 votes
What happens when we assign same values in two variables, is their address remains same?
Answeredchetan shidling asked 6 years ago • Python
1174 views2 answers0 votes
How to convert values of int and float into complex number in python?
Answeredchetan shidling asked 6 years ago • Python
1002 views1 answers0 votes
How to convert float value into int value in python?
Answeredchetan shidling asked 6 years ago • Python
988 views1 answers0 votes
Which of the following is not an objective for using Euler's path to draw stick diagrams?
Answeredcs asked 6 years ago • VLSI CMOS
818 views1 answers0 votes
Which of the following is not true about Latch-up in CMOS circuits?
Answeredcs asked 6 years ago • VLSI CMOS
793 views1 answers0 votes
In clocked CMOS logic, output in evaluated in?
Answeredcs asked 6 years ago • VLSI CMOS
1293 views1 answers0 votes
In the equivalent circuit for PMOS, if the sheet resistance is 20Kohm and width of MOS is 4, then the Drain-Source resistance when the PMOS is ON is numerically equal to?
Answeredcs asked 6 years ago • VLSI CMOS
907 views1 answers0 votes
Pseudo-nMOS has higher pull-up resistance than nMOS device?
Answeredcs asked 6 years ago • VLSI CMOS
840 views1 answers0 votes
Pull Down Network will conduct for all input combinations that requires output Y to be
Answeredcs asked 6 years ago • VLSI CMOS
862 views1 answers0 votes
What is RC Extraction in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
1090 views1 answers0 votes
What is full form of DRC in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
835 views1 answers0 votes
What is Latch-up in CMOS circuits?
Answeredcs asked 6 years ago • VLSI CMOS
860 views1 answers0 votes
What is precharge state in CMOS Dynamic logic?
Opencs asked 6 years ago • VLSI CMOS
797 views0 answers0 votes
What is evaluate state in CMOS Dynamic logic?
Opencs asked 6 years ago • VLSI CMOS
758 views0 answers0 votes
What is Clocked-CMOS logic?
Answeredcs asked 6 years ago • VLSI CMOS
1024 views1 answers-1 votes
Difference between dynamic and static logic design?
Answeredcs asked 6 years ago • VLSI CMOS
968 views1 answers0 votes
What is Pseudo NMOS logic in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
1058 views1 answers0 votes
What are the types of logic circuits in CMOS?
Answeredcs asked 6 years ago • VLSI CMOS
867 views1 answers0 votes
What type of MOS is preferable for PUN?
Opencs asked 6 years ago • VLSI CMOS
781 views0 answers0 votes
What type of MOS is preferable for PDN?
Opencs asked 6 years ago • VLSI CMOS
797 views0 answers0 votes
What is Complementary Logic design?
Answeredcs asked 6 years ago • VLSI CMOS
813 views1 answers0 votes
What is Complementary Logic design?
Opencs asked 6 years ago • VLSI CMOS
827 views0 answers0 votes
What is dynamic logic design?
Answeredcs asked 6 years ago • VLSI CMOS
1440 views1 answers0 votes
What is static logic design?
Answeredcs asked 6 years ago • VLSI CMOS
1438 views1 answers0 votes
What is combinational logic and non-regenerative circuits?
Answeredcs asked 6 years ago • VLSI CMOS
984 views1 answers0 votes
Can i get job after doing course of AWS?
Opencs asked 6 years ago • Cloud Computing
910 views0 answers0 votes
Why Ajax has been made?
Answeredcs asked 6 years ago • Web Development
845 views1 answers0 votes
What languages is AJAX a mixture of?
Answeredcs asked 6 years ago • Web Development
938 views1 answers0 votes
I want to make website, how to make?
Opencs asked 6 years ago • Web Development
840 views0 answers0 votes
« Previous 1…26 272829 30…36 Next »