Identify the step in a design flow that generates a Gate level net list?

All Questions › Category: VLSI CMOS › Identify the step in a design flow that generates a Gate level net list?

Chetan Shidling Staff asked 5 years ago

Options:

a. Synthesis
b. Simulation
c. Extraction
d. Floorplanning

1 Answers

Chetan Shidling Staff answered 5 years ago

Option a is the answer.