What is fall time in CMOS VLSI circuits ? All Questions › Category: VLSI CMOS › What is fall time in CMOS VLSI circuits ? 0 Vote Up Vote Down Chetan Shidling asked 4 years ago I need short information. 1 Answers 0 Vote Up Vote Down chetan shidling answered 4 years ago Fall time means the time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.