1 Answers
- Once the layout is made, there always is parasitic capacitances and resistances associated with the design.
- This is because of the compact layouts to make the chips smaller.
- These interferes in the functioning and performance of the circuit in terms of timing, speed and power consumption.
- We need to do Design-rule Verification.
- Tools – FastCap, FastHenry, Star-RCXT, QRC, Calibre xACT3D